GATE Technical: Electronics and Communications Engineering (EC) questions with solutions

Q1. Select the Boolean function(s) equivalent to x + yz, where x, y, and z are Boolean variables, and + denotes logical OR operation.

1. x + z + xy
2. (x + y)(x + z)
3. x + xy + yz
4. x + xz + xy

Answer: (x + y)(x + z)

The expression (x + y)(x + z) expands to x + xz + xy + yz, which simplifies to x + yz, demonstrating that it is equivalent to the original function.

Q2. Select the correct statement(s) regarding CMOS implementation of NOT gates.

1. Noise Margin High (NMH) is always equal to the Noise Margin Low (NML), irrespective of the sizing of transistors.
2. Dynamic power consumption during switching is zero.
3. For a logical high input under steady state, the nMOSFET is in the linear regime of operation.
4. Mobility of electrons never influences the switching speed of the NOT gate.

Answer: For a logical high input under steady state, the nMOSFET is in the linear regime of operation.

In a CMOS NOT gate, when a logical high input is applied, the nMOS transistor is turned on and operates in the linear region to effectively pull the output low, which is essential for the correct functioning of the gate.

Q3. For the circuit shown, the clock frequency is f0 and the duty cycle is 25%. For the signal at the Q output of the Flip-Flop, _______.

1. frequency is f0/4 and duty cycle is 50%
2. frequency is f0/4 and duty cycle is 25%
3. frequency is f0/2 and duty cycle is 50%
4. frequency is f0 and duty cycle is 25%

Answer: frequency is f0/2 and duty cycle is 50%

The Q output of the Flip-Flop toggles on every rising edge of the clock signal, which occurs at half the frequency of the input clock. Since the Flip-Flop captures the clock signal with a 25% duty cycle, the output will have a 50% duty cycle as it will be high for half of its period.