Exams › GATE › Technical

For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible. Which of the following statements is true?

1. (A) Q goes to 1 at the CLK transition and stays at 1.
2. (B) Q goes to 0 at the CLK transition and stays at 0.
3. (C) Q goes to 1 at the CLK transition and goes to 0 when D goes to 1.
4. (D) Q goes to 0 at the CLK transition and goes to 1 when D goes to 1.

Correct answer: (D) Q goes to 0 at the CLK transition and goes to 1 when D goes to 1.

Solution

The correct option is (D) because when the clock transitions from 1 to 0, the output Q captures the current state of D, which is 0. After this transition, when D changes to 1, Q will then update to reflect this new value.

Related GATE Technical questions

• Which of the following is NOT associated with a p-n junction?
• Which of the following is true?
• For static electric and magnetic fields in an inhomogeneous source-free medium, which of the following represents the correct form of two of Maxwell’s equations?
• For the circuit shown in the following figure, transistors M1 and M2 are identical NMOS transistors. Assume that M2 is in saturation and the output is unloaded. The current Ix is related to Ibias as
• A rectangular waveguide of internal dimensions (a = 4 cm and b = 3 cm) is to be operated in TE11 mode. The minimum operating frequency is
• One end of a loss-less transmission line having the characteristic impedance of 75Ω and length of 1 cm is short-circuited. At 3GHz, the input impedance at the other end of the transmission line is

⚔️ Practice GATE Technical free + battle 1v1 →