Exams › GATE › Technical

Let R and S be two relations with the following schema R(P, Q, R1, R2, R3) S(P, Q, S1, S2) where {P,Q} is the key for both schemas. Which of the following queries are equivalent? I. πP (R⋈S) II. πP (R) ⋈ πP (S) III. πP (πP,Q (R) ⋂ πP,Q (S)) IV. πP (πP,Q (R) − (πP,Q (R) − πP,Q (S)))

1. Only I and II
2. Only I and III
3. Only I, II and III
4. Only I, III and IV

Correct answer: Only I, III and IV

Solution

Options I, III, and IV are equivalent because they all yield the same result by focusing on the common key attributes P and Q from both relations R and S. Option I directly joins R and S and projects P, while III uses intersection to find common keys, and IV effectively retrieves the same keys by eliminating non-matching entries. Option II, however, does not guarantee the same result as it joins the projections of R and S separately, which may lead to different outcomes.

Related GATE Technical questions

• Let fsa and pda be two predicates such that fsa(x) means x is a finite state automaton and pda(y) means that y is a pushdown automaton. Let equivalent be another predicate such that equivalent(a,b) means a and b are equivalent. Which of the following first order logic statements represents the following: Each finite state automaton has an equivalent pushdown automaton.
• For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to
• Which of the following is/are true of the auto-increment addressing mode? I. It is useful in creating self-relocating code II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation III. The amount of increment depends on the size of the data item accessed
• Which of the following must be true for the RFE (Return from Exception) instruction on a general purpose processor? I. It must be a trap instruction II. It must be a privileged instruction III. An exception cannot be allowed to occur during execution of an RFE instruction
• For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary? I. L1 must be a write-through cache II. L2 must be a write-through cache III. The associativity of L2 must be greater than that of L1 IV. The L2 cache must be at least as large as the L1 cache
• In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is

⚔️ Practice GATE Technical free + battle 1v1 →