Exams › GATE › Technical

A binary baseband digital communication system employs the signal p(t) = { 1/√Tₛ, 0 ≤ t ≤ Tₛ { 0, otherwise for transmission of bits. The graphical representation of the matched filter output y(t) for this signal will be

1. (A) A rectangular pulse of height 1/Tₛ from t = 0 to t = 2Tₛ
2. (B) A trapezoidal waveform rising from 0 to 0.5, remaining constant till Tₛ, and falling to 0 at 2Tₛ
3. (C) A triangular waveform from t = 0 to 2Tₛ with peak value 1 at t = Tₛ
4. (D) A triangular waveform from t = 0 to Tₛ with peak value 1 at t = Tₛ/2

Correct answer: (C) A triangular waveform from t = 0 to 2Tₛ with peak value 1 at t = Tₛ

Solution

The correct option describes the output of the matched filter for a rectangular pulse input, which results in a triangular waveform due to the convolution of the pulse shape with itself. The peak occurs at the midpoint of the pulse duration, specifically at Tₛ, and the waveform extends from 0 to 2Tₛ, reflecting the integration of the signal over time.

Related GATE Technical questions

• The diodes D1 and D2 in the figure are ideal and the capacitors are identical. The product RC is very large compared to the time period of the ac voltage. Assuming that the diodes do not breakdown in the reverse bias, the output voltage V0 (in volt) at the steady state is ----------- The ac source is 10 sin ωt, connected between the left node and the midpoint of two identical capacitors C connected in series between the top and bottom rails. Ideal diode D1 is on the top rail from left to right, ideal diode D2 is on the bottom rail from left to right, and the load resistor R is connected between the top and bottom rails with V0 measured across R, positive at the top rail and negative at the bottom rail.
• In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in hex) and 0, respectively. If the instruction RLC is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be
• The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is
• The block diagram of a feedback control system is shown in the figure. The overall closed-loop gain G of the system is
• For the unity feedback control system shown in the figure, the open-loop transfer function G(s) is given as G(s) = 2 / (s(s+1)). The steady state error e_ss due to a unit step input is
• If a right-handed circularly polarized wave is incident normally on a plane perfect conductor, then the reflected wave will be

⚔️ Practice GATE Technical free + battle 1v1 →