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ExamsGATETechnical

The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-N counter (comprising ÷2, ÷4, ÷8, ÷16 outputs) is sketched below. The synthesizer is excited with a 5 kHz signal (input). The free-running frequency of the PLL is set to 20 kHz. Assume that the commutator switch makes contacts repeatedly in the order 1-2-3-4. The corresponding frequencies synthesized are:

  1. 10 kHz, 20 kHz, 40 kHz, 80 kHz
  2. 20 kHz, 40 kHz, 80 kHz, 160 kHz
  3. 80 kHz, 40 kHz, 20 kHz, 10 kHz
  4. 160 kHz, 80 kHz, 40 kHz, 20 kHz

Correct answer: 160 kHz, 80 kHz, 40 kHz, 20 kHz

Solution

The correct option is right because the divide-by-N counter outputs frequencies that are derived from the PLL's free-running frequency of 20 kHz. By dividing this frequency by 1, 2, 4, and 8, we obtain the synthesized frequencies of 20 kHz, 40 kHz, 80 kHz, and 160 kHz, respectively, in the order specified.

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