Exams › GATE › Technical
Statement for Linked Answer Questions 52 and 53:
A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.
What is the size of a page in KB in this computer?
- 2
- 4
- 8
- 16
Correct answer: 8
Solution
With a 4-byte PTE the entries per page are 2^(p-2), so each level uses p-2 index bits and the first-level table fits one page. The VPN has 46-p bits = 3(p-2), giving p=13, i.e. an 8 KB page. The stored 4 KB is wrong.
Related GATE Technical questions
⚔️ Practice GATE Technical free + battle 1v1 →