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Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions, I1, I2,..., I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the EI execution of this program, the time (in ns) needed to complete the program is

1. 132
2. 165
3. 176
4. 328

Correct answer: 165

Solution

The total time to complete the program is calculated by considering the pipeline stages and the delays, including the impact of the branch instruction. Since the branch is taken during the execution of I4, it causes a stall that adds extra cycles, resulting in a total time of 165 ns for the execution of all 12 instructions.

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