GATE Technical: Electronics and Communication Engineering (Set 2) questions with solutions

Q1. Which one of the following statements is correct about an ac-coupled common-emitter amplifier operating in the mid-band region?

1. The device parasitic capacitances behave like open circuits, whereas coupling and bypass capacitances behave like short circuits.
2. The device parasitic capacitances, coupling capacitances and bypass capacitances behave like open circuits.
3. The device parasitic capacitances, coupling capacitances and bypass capacitances behave like short circuits.
4. The device parasitic capacitances behave like short circuits, whereas coupling and bypass capacitances behave like open circuits.

Answer: The device parasitic capacitances behave like open circuits, whereas coupling and bypass capacitances behave like short circuits.

In the mid-band region, the frequency is high enough that the coupling and bypass capacitances effectively short-circuit AC signals, allowing them to pass through, while the parasitic capacitances of the device do not significantly affect the circuit and can be treated as open circuits.

Q2. Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

1. Widths of PMOS transistors should be doubled, while widths of NMOS transistors should be halved.
2. Widths of PMOS transistors should be doubled, while widths of NMOS transistors should not be changed.
3. Widths of PMOS transistors should be halved, while widths of NMOS transistors should not be changed.
4. Widths of PMOS transistors should be unchanged, while widths of NMOS transistors should be halved.

Answer: Widths of PMOS transistors should be doubled, while widths of NMOS transistors should not be changed.

In a NOR gate, the PMOS transistors need to provide sufficient drive strength to pull the output high, which is why their widths should be increased. Since NMOS transistors are already optimized for the original design, their widths can remain unchanged to maintain the same discharge characteristics.

Q3. An 8 Kbyte ROM with an active low Chip Select input (CS) is to be used in an 8085 microprocessor based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as A15 to A0, where A15 is the most significant address bit. Which of the following logic expressions will generate the correct CS signal for this ROM ?

1. A15 + A14 + (A13 · A12 + A13̅ · A12̅)
2. A15̅ · A14̅ · (A13 + A12̅)
3. A15̅ · A14̅ · (A13̅ · A12̅ + A13̅ · A12)
4. A15̅ + A14̅ + A13̅ · A12

Answer: A15 + A14 + (A13 · A12 + A13̅ · A12̅)

The 8KB span 1000H-2FFFH requires A15=0, A14=0 and A13 different from A12 (01 or 10). The active-low CS is A15+A14+(A13.A12 + A13'.A12'), which equals 0 (selected) exactly over that range; verified by full truth table.

Q4. The parallel-plate capacitor shown in the figure has movable plates. The capacitor is charged so that the energy stored in it is E when the plate separation is d. The capacitor is then isolated electrically and the plates are moved such that the plate separation becomes 2d. At this new plate separation, what is the energy stored in the capacitor, neglecting fringing effects?

1. 2E
2. √2E
3. E
4. E/2

Answer: 2E

After isolation the charge Q is fixed. C=eps*A/d halves when separation goes d->2d. Energy U=Q^2/(2C) therefore doubles to 2E (work done pulling the attracting plates apart). The stored sqrt(2)E is wrong; the answer is 2E.