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ExamsGATETechnical › Computer Science and Information Technology Set 2 (CS 2)

GATE Technical: Computer Science and Information Technology Set 2 (CS 2) questions with solutions

5 questions with worked solutions.

Questions

Q1. Once the DBMS informs the user that a transaction has been successfully completed, its effect should persist even if the system crashes before all its changes are reflected on disk. This property is called

  1. durability
  2. atomicity
  3. consistency
  4. isolation

Answer: durability

Durability ensures that once a transaction is confirmed as complete, its effects are permanently recorded in the database, even in the event of a system failure, thus maintaining data integrity.

Q2. In the context of owner and weak entity sets in the E R (Entity-Relationship) data model, which one of the following statements is TRUE?

  1. The weak entity set MUST have total participation in the identifying relationship
  2. The owner entity set MUST have total participation in the identifying relationship
  3. Both weak and owner entity sets MUST have total participation in the identifying relationship
  4. Neither weak entity set nor owner entity set MUST have total participation in the identifying relationship

Answer: The weak entity set MUST have total participation in the identifying relationship

A weak entity set relies on its owner entity set for its identification, which necessitates that it participates fully in the identifying relationship to ensure that every instance of the weak entity can be uniquely identified.

Q3. Node X has a TCP connection open to node Y. The packets from X to Y go through an intermediate IP router R. Ethernet switch S is the first switch on the network path between X and R. Consider a packet sent from X to Y over this connection. Which of the following statements is/are TRUE about the destination IP and MAC addresses on this packet at the time it leaves X?

  1. The destination IP address is the IP address of R
  2. The destination IP address is the IP address of Y
  3. The destination MAC address is the MAC address of S
  4. The destination MAC address is the MAC address of Y

Answer: The destination IP address is the IP address of Y

The destination IP address is the address of the final destination, which is node Y, as the packet is routed based on the IP address to reach its intended recipient.

Q4. Let M be the 5-state NFA with ε-transitions shown in the diagram below. Which one of the following regular expressions represents the language accepted by M ?

  1. (00)* + 1(11)*
  2. 0* + (1 + 0(00)*)(11)*
  3. (00)* + (1 + (00)*)(11)*
  4. 0* + 1(11)* + 0(11)*

Answer: 0* + (1 + 0(00)*)(11)*

The correct option accurately captures the language accepted by the NFA by allowing for any number of leading zeros, followed by either a single '1' or a sequence starting with '0' followed by any number of '00's, and concluding with any number of '11's. This structure reflects the transitions and states of the NFA, ensuring all valid strings are included.

Q5. Consider a multi-threaded program with two threads T1 and T2. The threads share two semaphores: s1 (initialized to 1) and s2 (initialized to 0). The threads also share a global variable x (initialized to 0). The threads execute the code shown below. // code of T1 wait(s1); x = x+1; print(x); wait(s2); signal(s1); // code of T2 wait(s1); x = x+1; print(x); signal(s2); signal(s1); Which of the following outcomes is/are possible when threads T1 and T2 execute concurrently?

  1. T1 runs first and prints 1, T2 runs next and prints 2
  2. T2 runs first and prints 1, T1 runs next and prints 2
  3. T1 runs first and prints 1, T2 does not print anything (deadlock)
  4. T2 runs first and prints 1, T1 does not print anything (deadlock)

Answer: T1 runs first and prints 1, T2 does not print anything (deadlock)

The correct option describes a scenario where T1 successfully increments and prints the value of x before waiting on s2, which is not signaled by T2. Since T2 cannot proceed without the signal from T1, it leads to a deadlock situation where T2 is blocked and cannot print anything.

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