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ExamsGATEEngineering Mathematics

Statement for Linked Answer Questions 54 and 55: A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is

  1. (A) 11
  2. (B) 14
  3. (C) 16
  4. (D) 27

Correct answer: (B) 14

Solution

To determine the number of bits in the tag field, we first calculate the total number of cache lines, which is derived from the cache size and block size. With a 256 KByte cache and a block size of 32 Bytes, there are 8192 blocks. Since it's a 4-way set associative cache, we have 2048 sets. The address consists of 32 bits, and we need to account for the index (11 bits for 2048 sets) and the block offset (5 bits for 32 Bytes), leaving us with 14 bits for the tag.

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